1. Technical Field
The invention relates to a printed circuit board, a method of manufacturing the printed circuit board, and an apparatus for perforating via holes.
2. Description of the Related Art
With developments in the electronics industry, electronic parts, including cell phones, have become smaller and have provided more functionality, which has led to an increasing demand for smaller and denser printed circuit boards having finer patterns. In step with this trend towards denser printed circuit boards having finer patterns, the diameters of vias used for interlayer connection in a printed circuit board are also becoming finer, entailing greater levels of precision.
To implement interlayer connection in a printed circuit board using micro vias, precision alignment is required between an upper and lower layer, with low relative eccentricity between the upper and lower layers.
FIG. 1 is a cross-sectional view of a printed circuit board according to prior art, and FIG. 2 is a cross-sectional view of a via formed according to prior art. In FIGS. 1 and 2 are illustrated an insulation substrate 102, an insulation layer 104, circuit patterns 106, a reference mark 108, a via land 110, a copper foil layer 112, a window 114 for forming the via hole, and a via hole 116.
A method of manufacturing a printed circuit board according to prior art includes first forming a circuit pattern 106 on the lower surface of an insulation substrate 102, forming a circuit pattern 106, including via-lands 110, on the upper surface of the insulation substrate 102, and then stacking an insulation layer 104 on the upper surface of the insulation substrate 102 and stacking a copper foil layer 112 on top.
When the copper foil layer 112 has been stacked, it is selectively etched to form a reference mark 108. After determining the opening position of the window 114 for forming the via hole based on the reference mark 108 and opening the window 114 accordingly, the via hole 116 is formed from the window 114. Then, plating is performed in the via hole 116 to form a via 103.
When the via 103 has been formed, the copper foil layer 112 is selectively etched to form a circuit pattern 106 on the upper surface of the insulation layer 104.
However, with this method of forming a via 103 according to prior art, the reference mark 108 formed on the copper foil layer 112 is recognized first and then the via hole 116 is perforated based on this reference mark 108, so that when eccentricity is created during the process of manufacturing the printed circuit board due to differences in the amount of expansion and contraction between the insulation substrate 102 and the insulation layer 104, the via land 110 formed on the insulation substrate 102 is moved in relation to the insulation layer 104, whereby perforating the via hole 116 based on the reference mark 108 formed on the upper surface of the insulation layer 104 causes the via hole 116 to deviate from the via land 110. Afterwards, when plating is performed or conductive paste is filled in the via hole 116 deviating from the via land 110, the via 103 may be formed in an undesirable position, as shown in FIG. 2, or short-circuiting may occur, so that the manufacturing yield may be decreased.